1. Field of the Invention
The present invention relates to a Field Programmable Gate Array (FPGA) device.
2. Description of the Related Art
The FPGA devices are programmable logic devices that provide an array of generic combinational and/or sequential logic elements that can be programmed and interconnected to each other by the user to realize a wide variety of logic circuit designs.
Many of the new FPGA architectures are based on semiconductor memory technology, and particularly on electrically alterable semiconductor memories, making use of floating gate MOSFETs and RAM cells; this means that a new computational architecture can be implemented by the FPGA device by simply re-programming the logic functions and interconnection routing on the chip.
Although FPGA devices have been traditionally used to integrate glue logic, the interest towards the possible applications of the FPGA devices is increasingly growing because of their short development time, low costs of production and request of few resources dedicated to simulation and to re-programmability during project flow and utilization. Thanks to their great flexibility, the FPGA devices are gaining more visibility, for example, in telecommunications and networking, where however also a high operation speed is very attractive.
Referring to FIG. 1A, a schematic block diagram of an exemplary FPGA device 100 is shown. The FPGA device 100 is provided with a plurality of programmable input/output blocks (IOB) 105 for receiving/sending signals, and a plurality of programmable logic blocks (LB) 110, comprising combinational and/or sequential logic elements. The FPGA device 100 includes electrical interconnection segments (conductive lines) 115 and programmable switch blocks (SB) 120 for activating/de-activating interconnections between the blocks 105, 110.
The switch blocks 120 include a plurality of controlled electronic switches, such as voltage controlled MOS transistors in transmission gate configuration (often called pass transistors). The controlled electronic switches are connected between two or more conductive lines 115, which are connected to the blocks 105, 110 and/or to further switch blocks 120. The plurality of electronic switches is disposed in such a way that it is possible to configure different paths of interconnections; consequently, the input/output blocks 105 are connectable to desired logic blocks 110, and predetermined logic blocks 110 are connectable to specified further logic blocks 110. In particular, each electronic switch is controlled by respective control signals, provided by a FPGA control unit 125, for activating/de-activating the selected interconnections; in this way, it is possible to implement a given function by properly connecting to each other desired blocks 105, 110, and it is possible to properly program the FPGA device 100 so as to permit the execution of required operations.
As depicted schematically in FIG. 1B, the control unit 125, embedded in the FPGA device 100 (i.e., integrated in a same semiconductor chip with the input/output blocks 105, the logic blocks 110, the interconnection segments 115 and the switch blocks 120), typically comprises a volatile memory device 135 for storing configuration logic values corresponding to the open status or the closed status of each electronic switch of the switch blocks 120. The volatile memory device 135, preferably a Static RAM memory (SRAM-based FPGA device), may consist in a two-dimensional arrangement (a matrix) of a plurality of volatile memory cells. Each volatile memory cell provides the respective control signal to at least one electronic switch, accordingly to the stored configuration logic value, for activating/de-activating the selected interconnections of the FPGA device 100.
The possibility of re-programming the volatile memory device (a RAM memory can be re-configured dynamically) permits new configurations of the interconnections of the FPGA device 100. However, the configuration logic values cannot be preserved in a volatile memory device during stand-by or, generally, when the device is not powered. Non-volatility is desirable for many applications of the FPGA devices, but a non-volatile memory device, such as a flash memory implemented by floating gate transistors, has a longer access time and greater power consumption than a volatile memory device.
For benefiting of the different properties of both volatile and non-volatile memories, the FPGA device 100 is usually associated with a non-volatile memory device 130 (schematically shown in dash-and-dot lines in FIG. 1B); a stand-alone memory integrated in a chip different than that of the FPGA device, for storing the configuration logic values also during stand-by or power-down. In this way, the non-volatile memory device 130 acts as a back-up storage unit in respect of the volatile memory device 135.
The non-volatile memory device 130, preferably an electrically alterable memory device (for example, a flash memory), non-volatily stores information corresponding to the configuration logic values for the electronic switches. At the power-on of the FPGA device 100 a power-on circuit 140, depicted in FIG. 1B as included in the FPGA control unit 125, enables the transfer of the information stored in the non-volatile memory device 130 into the volatile memory device 135. Accordingly to the stored configuration logic value, each volatile memory cell provides the control signal to the respective electronic switch.
The use of two different semiconductor chips, one for the FPGA device and one for the back-up non-volatile memory device, is disadvantageous, because very complex and expensive. A wide area on the printed circuit board is to be reserved and interconnections between the two chips are to be provided.